1. Field of the Invention
This invention relates, in general, to digital signal processing systems and, more specifically, to storage controllers which control the transfer of data in a digital signal processing system comprising at least a memory device, a plurality of input/output devices and a digital signal processor.
2. Description of the Prior Art
In signal processing systems, special purpose digital signal processors have been used to process digital data such as a series of data words obtained by sampling an analog signal and converting the sample with an analog to digital converter to a digital word. In such systems, the digital signal processor performs complex arithmetic computations, such as a Fast Fourier Transform (FFT), on blocks or vectors of digital data words obtained from the analog signals for use in frequency spectrum analysis and filtering applications. One such digital signal processor is disclosed in U.S. Pat. No. 3,812,470, issued to J. Murtha and J. Ross and assigned to the assignee of the present invention. The digital signal processor disclosed therein is efficiently designed to perform a Fast Fourier Transform on a block of data words. As is generally known, each stage of a N-point FFT involves several complex additions and multiplications in order to generate both the real and imaginary coefficients of the transform. Thus, it is apparent that as the number of data points sampled increase so must the number of operations to be performed by the digital signal processor. When large data sets are to be processed, the throughput of the special purpose digital signal processor is greatly decreased since the processor must store and handle all of the data transfers and further must generate the complex strings of memory addresses needed to formulate the data so as to efficiently compute the transform.
A typical prior art approach to improve the throughput of a processor utilizes a so-called input-output controller which independently handles the transfer of data between a central processing unit, for example, and a number of input-output devices thereby relieving the central processor of the time consuming task of communicating with each device. One such system is disclosed in U.S. Pat. No. 3,740,728, issued to Pullen, in which the central processor initiates a data transfer by sending to the input-output controller the first word in memory of the data transfer, the number of data words to be transferred, the specific input-output device involved and the direction of data transfer. The input-output controller then completely controls the data transfer by generating a consecutive sequence of memory addresses, transfers the data, word by word, between the input-output device and each address location in memory and finally tells the central processor when the data transfer is finished.
In a similar system, disclosed in U.S. Pat. No. 3,413,716, issued to Bahrs, a memory controller coordinates access to a memory by recognizing requests for data transfer from both a central processing unit and a plurality of input-output controllers according to a predetermined priority scheme. Each input-output controller independently controls the transfer of data between the memory controller and a plurality of input-output devices connected thereto.
Such input-output controllers greatly increase the throughput of a central processing unit by relieving the central processor of the time consuming task of controlling each data transfer with input-output devices which are generally slow electromechanical devices. However, such systems provide no capability for generating the complex, non-sequential strings of memory addresses necessary to formulate the data so as to efficiently perform complex arithmetic functions, such as a Fast Fourier Transform, since such input-output controllers known in the prior art merely transfer blocks of data between consecutive address locations in the memory.
Thus, it is desirable to provide a controller for a digital signal processing system which is capable of independently initiating and controlling the transfer of vectors or blocks of data between a digital signal processor and a plurality of input-output devices. It is also desirable to provide a controller which has the capability to generate complex, non-sequential strings of memory addresses useful in performing complex arithmetic functions, such as a Fast Fourier Transform. In addition, it is desirable to provide a controller which is able to recognize requests for data transfer from each device and further is able to initiate transfer of vectors of data according to a predetermined priority scheme in order to maximize the overall system processing capability.